- Responsible for the design and development of analog building blocks, including amplifiers, integrators, switched capacitor circuits, regulators, bandgap circuits, Delta-Sigma ADCs, SAR ADCs, filters and control logics etc.
- Responsible for top-level integration of high performance mixed signal chips including analog front end signal acquisition and conditioning chips and analog front end battery monitor chips etc.
- Study and do research on block level architectures for different analog block circuity to meet system performance requirements.
- Perform block level analog circuit design analysis, modelling, simulation and test chip validation.
- Execute schematic design, corner simulation, extraction parasitic simulation and debug.
- Work with layout engineer to achieve optimized block level layout with LVS/DRC clean.
- Work with other engineers to achieve full chip integration, physical implementation, tape out and testchip validation.
- Bachelor/Master/PhD in Electrical/Electronic Engineering with 5+ years of related experience is preferred but new college graduates will be considered
- In depth knowledge on different types of Analog circuit design and architecture.
- Proficient with Cadence Analog IC design, simulation, layout tools.
- Good knowledge of ADC, LNA, analog multiplexer, filter, bandgap.
Please send your resume in WORD format by clicking the apply button below or contact Catherine QU on +65 9645 9680 for a confidential discussion. Please note that only short-listed candidates will be contacted. CEI Reg. Number R22104823 (QU QIUSHI).