Responsibilities:
- Block-level architecture definition and design
- Writing design spec and report
- Block-level RTL implementation
- SOC integration
- Simulation/Verification at both block-level and system level
- Block-level synthesis and timing analysis
- FPGA/silicon validation on related modules
- Spec & micro-architecture definition based on C/C++/SystemC algorithm model.
Requirements:
- MSEE degree with 1~8 years' experience
- Solid knowledge of digital design building blocks (Data-path, Filters, FIFO...)
- Strong skills in Verilog RTL coding, verification, and debugging.
- SOC/FPGA design/validation experience
- Experience in digital signal processing design is a strong plus.
- Familiar one of the following is a plus, USB/SDIO/Audio
- Familiar with System-Verilog language is a plus.
Please send your resume in WORD format by clicking the apply button below or contact Catherine QU on +65 9645 9680 for a confidential discussion. Please note that only short-listed candidates will be contacted. CEI Reg. Number R22104823 (QU QIUSHI).
