Digital Design Engineer

  • Location


  • Sector:

  • Job type:


  • Salary:

    S$7000 - S$14000 per annum

  • Contact:

    Catherine Qu

  • Contact email:

  • Job ref:


  • Published:

    about 1 month ago

  • Expiry date:


  • Consultant:



  1. Block-level architecture definition and design
  2. Writing design spec and report
  3. Block-level RTL implementation
  4. SOC integration
  5. Simulation/Verification at both block-level and system level
  6. Block-level synthesis and timing analysis
  7. FPGA/silicon validation on related modules
  8. Spec & micro-architecture definition based on C/C++/SystemC algorithm model.


  1. MSEE degree with 1~8 years' experience
  2. Solid knowledge of digital design building blocks (Data-path, Filters, FIFO...)
  3. Strong skills in Verilog RTL coding, verification, and debugging.
  4. SOC/FPGA design/validation experience
  5. Experience in digital signal processing design is a strong plus.
  6. Familiar one of the following is a plus, USB/SDIO/Audio
  7. Familiar with System-Verilog language is a plus.

Please send your resume in WORD format by clicking the apply button below or contact Catherine QU on +65 9645 9680 for a confidential discussion. Please note that only short-listed candidates will be contacted. CEI Reg. Number R22104823 (QU QIUSHI).