Design Verification Engineer
Our client is a young and ambitious SoC design house who dedicated to wireless area. To expand their R&D team and explore overseas market, they are now looking for various design talents in Singapore.
Responsibilities:
- You will responsible for verification platform setup, compile and certificate automated scripts, accelerate and automize verification processes.
- You will create, monitor and execute chip verification plan, you will get involved in system-level verification, module-level verification and post simulation;
- You will do trouble shooting on tools and environments during chip verification.
Requirements:
To be considered with this role, you will be proficient in Linux/Unix, you will be sophisticated with Perl/Python, C/C++ and Unix Shell script languages;
You will be proficient in Verilog and System Verilog languages; you will be sophisticated using major EDA Simulation tools like VCS, Verdi etc.
You will be proficient in chip verification process and UVM verification methodology, you will be experienced with verification platform setup by using UVM+SystemVerilog;
You will be capable of writing technical texts.
You will have at least 3 years experiences of design or verification, with at least 1 ASIC/SOC projects tape-out;
Experience with Ethernet physical-layer protocols, Serdes physical-layer protocols will be highly referred.
Please send your resume in WORD format by clicking the apply button below or contact Catherine QU on +65 9645 9680 for a confidential discussion. Please note that only short-listed candidates will be contacted. CEI Reg. Number R22104823 (QU QIUSHI).
Please send your resume in WORD format by clicking the apply button below or contact Catherine Qu on +65 6701 1522 for a confidential discussion. Please note that only short-listed candidates will be contacted.CEI Reg. Number R22104823 (Qi Qiushi).
