Digital Backend Design Engineer
Our client is a young and ambitious SoC design house who dedicated to wireless area. To expand their R&D team and explore overseas market, they are now looking for various design talents in Singapore.
Responsibilities:
To provide physical design of top-level SoC and back-end design including FlooPlan, APR, CTS, etc.
To do physical verification, including DRC, LVS, ERC;
To work with front-end team on STA, power analysis, SI analysis, and optimization of timing, power, and area.
To export GDS and finish tape-out.
Requirements
To be considered with this role, you will hold at least bachelor degree of either Electronics Engineering, or Communication, or Computer Science or other relative fields;
You will be sophisticated with back-end EDA tools, and back-end design processes;
You will be proficient in scripting e.g. perl/tcl/shell, etc;
You will be proficient in TimingECO and can be deeply involved into STA analysis in projects;
Experiences with 28nm/16nm/14nm layout design would be highly preferred;
Fluent English speaking, mandarin speaking highly preferred because internal stakeholders are mandarin speakers.
Please send your resume in WORD format by clicking the apply button below or contact Catherine QU on +65 9645 9680 for a confidential discussion. Please note that only short-listed candidates will be contacted. CEI Reg. Number R22104823 (QU QIUSHI).
Please send your resume in WORD format by clicking the apply button below or contact Catherine Qu on +65 6701 1522 for a confidential discussion. Please note that only short-listed candidates will be contacted.CEI Reg. Number R22104823 (Qi Qiushi).
